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1/29 preliminary data january 2001 this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change without notice. m29w160dt M29W160DB 16 mbit (2mb x8 or 1mb x16, boot block) 3v supply flash memory features summary n single 2.7 to 3.6v supply voltage for program, erase and read operations n access time: 70ns n programming time 10 m s per byte/word typical n 35 memory blocks 1 boot block (top or bottom location) 2 parameter and 32 main blocks n program/erase controller embedded program and erase algorithms n erase suspend and resume modes read and program another block during erase suspend n unlock bypass program command faster production/batch programming n temporary block unprotection mode n security memory block n low power consumption standby and automatic standby n 100,000 program/erase cycles per block n electronic signature manufacturer code: 0020h top device code m29w160dt: 22c4h bottom device code M29W160DB: 2249h figure 1. packages 44 1 tsop48 (n) 12 x 20mm so44 (m) lfbga48 (za) 8 x 6 solder balls fbga
m29w160dt, M29W160DB 2/29 table of contents summary description . . . . . . . . ........................................... ........5 logic diagram . ......................... ................................ ........5 signal names . ......................... ................................ ........5 tsop connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ............6 so connections . . . . . . . . . .......................................................6 lfbga connections (top view through package) . . . . . . . ...............................7 table 2. top boot block addresses, m29w160dt. . ....................................8 table 3. bottom boot block addresses, M29W160DB . . . . . . . . . . . . . . . . . . . . ...............8 signal descriptions . . ..........................................................9 address inputs (a0-a19). . . . . . . ...................................................9 data inputs/outputs (dq0-dq7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 data inputs/outputs (dq8-dq14). . . . . . . . . . . . . . .....................................9 data input/output or address input (dq15a-1). . . . .....................................9 chip enable (e). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...............................9 output enable (g). . . . . . . . . . . . . . . . ...............................................9 write enable (w). . . . . . . . . . . . . ........................................... ........9 reset/block temporary unprotect (rp). . . ............................................9 ready/busy output (rb). . . . . . . ........................................... ........9 byte/word organization select (byte). . . . . . . . . ......................................9 v cc supply voltage. . . . . . . . . . . . . . . . . . ............................................9 vss ground.. . ..................................................................9 bus operations. . . . . . . . . . . . . . ........................................... .......10 bus read. . . . . . . . . . . . . . . . . . . . . . . . . . ...........................................10 bus write. ............................. ................................ .......10 output disable. . . ..............................................................10 standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..............................10 automatic standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .................................10 special bus operations. .........................................................10 electronic signature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 block protection and blocks unprotection. ...........................................10 table 4. bus operations, byte = v il ........................................ .......10 table 5. bus operations, byte = v ih ...............................................11 command interface . . . . . . . . . . . . . . . . ...........................................11 read/reset command.. . . . . . . . . . . . . . . . . . . . . . ....................................11 auto select command. . . . .......................................................11 program command. . . . . . . . . . . . . . . . . . . . . . . . . . ...................................11 unlock bypass command. . . . . . ..................................................12 unlock bypass program command. . . . . . . . . . . . . . . . .................................12 unlock bypass reset command. . . . . . . . . . . . . . . . . . .................................12 chip erase command. . . . . ......................................................12 block erase command.. .........................................................12
3/29 m29w160dt, M29W160DB erase suspend command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .......................12 erase resume command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...........13 security data command. . . . . . . . . . . . . . ...........................................13 table 6. security memory block addresses . . . .......................................13 table 7. commands, 16-bit mode, byte = v ih .......................................14 table 8. commands, 8-bit mode, byte = v il .........................................15 table 9. program, erase times and program, erase endurance cycles . . . . . . . . . . . . . . . . . . . . 16 status register . . . . . . . . . . . . . ..................................................16 data polling bit (dq7). . . . . ......................................................16 toggle bit (dq6).. . . . . . .........................................................16 error bit (dq5). . . ..............................................................16 erase timer bit (dq3). . . . . . . . . . . . . . . . . . . . . . . . . . .................................17 alternative toggle bit (dq2).. . . ............................. ......................17 table 10. status register bits . . . . . . . . . . . . . . . . . . ............................... ....17 figure 6. data polling flowchart . ........................................... .......18 figure 7. data toggle flowchart . . . . . . . . ...........................................18 maximum rating. . . . . . . . . . . . . . . . . . . . . ...........................................18 absolute maximum ratings. . . . . . . . . . . . . . . . . . . . . . .................................18 dc and ac parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . ..............................19 operating and ac measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 ac measurement i/o waveform . ..................................................19 ac measurement load circuit . . ........................................... .......19 capacitance. . . . . . . . . . . . .......................................................19 dc characteristics. . . . . . . . . . . . . . . . . . . ...........................................20 read mode ac waveforms. ......................................................21 read ac characteristics .........................................................21 write ac waveforms, write enable controlled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...........22 write ac characteristics, write enable controlled . . ............................... ....22 write ac waveforms, chip enable controlled . . . . ............................. .......23 write ac characteristics, chip enable controlled . . . . . . . . . . . . . . .......................23 reset/block temporary unprotect ac waveforms . . . . . . . . . . . . . . . . . . . . . . . ..............24 reset/block temporary unprotect ac characteristics . . . . . . . . . . . . . . . . ..................24 package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 tsop48 - 48 lead plastic thin small outline, 12 x 20mm, package outline . . . . . . ...........25 tsop48 - 48 lead plastic thin small outline, 12 x 20mm, package mechanical data . . . . . . . . . 25 so44 - 44 lead plastic small outline, 525 mils body width, package outline . . . . . . . . . . . . ....26 lfbga48 - 8 x 6 balls, 0.80 mm pitch, bottom view package outline ......................27 lfbga48 - 8 x 6 balls, 0.80mm pitch, package mechanical data . . . ......................27 part numbering . . . . . . . . . ......................................................28 ordering information scheme . . . . . . . . . . . . . . . . . ....................................28
m29w160dt, M29W160DB 4/29 revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . ....................................28 document revision history ................................. ......................28
5/29 m29w160dt, M29W160DB summary description the m29w160d is a 16 mbit (2mb x8 or 1mb x16) non-volatile memory that can be read, erased and reprogrammed. these operations can be per- formed using a single low voltage (2.7 to 3.6v) supply. on power-up the memory defaults to its read mode where it can be read in the same way as a rom or eprom. the memory is divided into blocks that can be erased independently so it is possible to preserve valid data while old data is erased. each block can be protected independently to prevent accidental program or erase commands from modifying the memory. program and erase commands are writ- ten to the command interface of the memory. an on-chip program/erase controller simplifies the process of programming or erasing the memory by taking care of all of the special operations that are required to update the memory contents. the end of a program or erase operation can be detected and any error conditions identified. the command set required to control the memory is consistent with jedec standards. the blocks in the memory are asymmetrically ar- ranged, see tables 2 and 3, block addresses. the first or last 64 kbytes have been divided into four additional blocks. the 16 kbyte boot block can be used for small initialization code to start the micro- processor, the two 8 kbyte parameter blocks can be used for parameter storage and the remaining 32k is a small main block where the application may be stored. chip enable, output enable and write enable sig- nals control the bus operation of the memory. they allow simple connection to most micropro- cessors, often without additional logic. the memory is offered in tsop48 (12 x 20mm), so44 and lfbga48 (0.8mm pitch) packages and it is supplied with all the bits erased (set to '1'). figure 2. logic diagram note: rb not available on so44 package. table 1. signal names ai03843 20 a0-a19 w dq0-dq14 v cc m29w160dt M29W160DB e v ss 15 g rp dq15a1 byte rb a0-a19 address inputs dq0-dq7 data inputs/outputs dq8-dq14 data inputs/outputs dq15a1 data input/output or address input e chip enable g output enable w write enable rp reset/block temporary unprotect rb ready/busy output (not available on so44 package) byte byte/word organization select v cc supply voltage v ss ground nc not connected internally du don't use as internally connected
m29w160dt, M29W160DB 6/29 figure 3. tsop connections figure 4. so connections dq3 dq9 dq2 a6 dq0 w a3 rb dq6 a8 a9 dq13 a17 a10 dq14 a2 dq12 dq10 dq15a1 v cc dq4 dq5 a7 dq7 nc nc ai03844 m29w160dt M29W160DB 12 1 13 24 25 36 37 48 dq8 nc a19 a1 a18 a4 a5 dq1 dq11 g a12 a13 a16 a11 byte a15 a14 v ss e a0 rp v ss g dq0 dq8 a3 a0 e v ss a2 a1 a13 v ss a14 a15 dq7 a12 a16 byte dq15a1 dq5 dq2 dq3 v cc dq11 dq4 dq14 a9 a19 rp a4 w a7 ai03845 m29w160dt M29W160DB 8 2 3 4 5 6 7 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 20 19 18 17 dq1 dq9 a6 a5 dq6 dq13 44 39 38 37 36 35 34 33 a11 a10 dq10 21 dq12 40 43 1 42 41 a17 a8 a18
7/29 m29w160dt, M29W160DB figure 5. lfbga connections (top view through package) ai02985b 6 5 4 3 2 1 v ss dq15 a1 a15 a14 a12 a13 dq3 dq11 dq10 a18 du rb dq1 dq9 dq8 dq0 a6 a17 a7 g e a0 a4 a3 dq2 dq6 dq13 dq14 a10 a8 a9 dq4 v cc dq12 dq5 a19 du rp w a11 dq7 a1 a2 v ss a5 du a16 byte g f e b a d c h
m29w160dt, M29W160DB 8/29 table 2. top boot block addresses, m29w160dt table 3. bottom boot block addresses, M29W160DB # size (kbytes) address range (x8) address range (x16) 34 16 1fc000h-1fffffh fe000h-fffff h 33 8 1fa000h-1fbfffh fd000h-fdfffh 32 8 1f8000h-1f9fffh fc000h-fcfffh 31 32 1f0000h-1f7fffh f8000h-fbfffh 30 64 1e0000h-1effffh f0000h-f7fffh 29 64 1d0000h-1dffffh e8000h-effffh 28 64 1c0000h-1cffffh e0000h-e7fffh 27 64 1b0000h-1bffffh d8000h-dffffh 26 64 1a0000h-1affffh d0000h-d7fffh 25 64 190000h-19ffffh c8000h-cffffh 24 64 180000h-18ffffh c0000h-c7fffh 23 64 170000h-17ffffh b8000h-bffffh 22 64 160000h-16ffffh b0000h-b7fffh 21 64 150000h-15ffffh a8000h-affffh 20 64 140000h-14ffffh a0000h-a7fffh 19 64 130000h-13ffffh 98000h-9ffffh 18 64 120000h-12ffffh 90000h-97fffh 17 64 110000h-11ffffh 88000h-8ffffh 16 64 100000h-10ffffh 80000h-87fffh 15 64 0f0000h-0fffffh 78000h-7ffffh 14 64 0e0000h-0effffh 70000h-77fffh 13 64 0d0000h-0dffffh 68000h-6ffffh 12 64 0c0000h-0cffffh 60000h-67fffh 11 64 0b0000h-0bffffh 58000h-5ffffh 10 64 0a0000h-0affffh 50000h-57fffh 9 64 090000h-09ffffh 48000h-4ffffh 8 64 080000h-08ffffh 40000h-47fffh 7 64 070000h-07ffffh 38000h-3ffffh 6 64 060000h-06ffffh 30000h-37fffh 5 64 050000h-05ffffh 28000h-2ffffh 4 64 040000h-04ffffh 20000h-27fffh 3 64 030000h-03ffffh 18000h-1ffffh 2 64 020000h-02ffffh 10000h-17fffh 1 64 010000h-01ffffh 08000h-0ffffh 0 64 000000h-00ffffh 00000h-07fffh # size (kbytes) address range (x8) address range (x16) 34 64 1f0000h-1fffffh f8000h-fffffh 33 64 1e0000h-1effffh f0000h-f7fffh 32 64 1d0000h-1dffffh e8000h-effffh 31 64 1c0000h-1cffffh e0000h-e7fffh 30 64 1b0000h-1bffffh d8000h-dffff h 29 64 1a0000h-1affffh d0000h-d7fffh 28 64 190000h-19ffffh c8000h-cffff h 27 64 180000h-18ffffh c0000h-c7fffh 26 64 170000h-17ffffh b8000h-bffffh 25 64 160000h-16ffffh b0000h-b7fffh 24 64 150000h-15ffffh a8000h-affffh 23 64 140000h-14ffffh a0000h-a7fffh 22 64 130000h-13ffffh 98000h-9ffff h 21 64 120000h-12ffffh 90000h-97fffh 20 64 110000h-11ffffh 88000h-8ffff h 19 64 100000h-10ffffh 80000h-87fffh 18 64 0f0000h-0fffffh 78000h-7ffff h 17 64 0e0000h-0effffh 70000h-77fffh 16 64 0d0000h-0dffffh 68000h-6ffff h 15 64 0c0000h-0cffffh 60000h-67fffh 14 64 0b0000h-0bffffh 58000h-5ffff h 13 64 0a0000h-0affffh 50000h-57fffh 12 64 090000h-09ffffh 48000h-4ffff h 11 64 080000h-08ffffh 40000h-47fffh 10 64 070000h-07ffffh 38000h-3ffff h 9 64 060000h-06ffffh 30000h-37fffh 8 64 050000h-05ffffh 28000h-2ffff h 7 64 040000h-04ffffh 20000h-27fffh 6 64 030000h-03ffffh 18000h-1ffff h 5 64 020000h-02ffffh 10000h-17fffh 4 64 010000h-01ffffh 08000h-0ffff h 3 32 008000h-00ffffh 04000h-07fffh 2 8 006000h-007fffh 03000h-03fffh 1 8 004000h-005fffh 02000h-02fffh 0 16 000000h-003fffh 00000h-01fffh
9/29 m29w160dt, M29W160DB signal descriptions see figure 2, logic diagram, and table 1, signal names, for a brief overview of the signals connect- ed to this device. address inputs (a0-a19). the address inputs select the cells in the memory array to access dur- ing bus read operations. during bus write opera- tions they control the commands sent to the command interface of the internal state machine. data inputs/outputs (dq0-dq7). the data in- puts/outputs output the data stored at the selected address during a bus read operation. during bus write operations they represent the commands sent to the command interface of the internal state machine. data inputs/outputs (dq8-dq14). the data in- puts/outputs output the data stored at the selected address during a bus read operation when byte is high, v ih . when byte is low, v il , these pins are not used and are high impedance. during bus write operations the command register does not use these bits. when reading the status register these bits should be ignored. data input/output or address input (dq15a-1). when byte is high, v ih , this pin behaves as a data input/output pin (as dq8-dq14). when byte is low, v il , this pin behaves as an address pin; dq15a1 low will select the lsb of the word on the other addresses, dq15a1 high will select the msb. throughout the text consider references to the data input/output to include this pin when byte is high and references to the address in- puts to include this pin when byte is low except when stated explicitly otherwise. chip enable (e). the chip enable, e, activates the memory, allowing bus read and bus write op- erations to be performed. when chip enable is high, v ih , all other pins are ignored. output enable (g). the output enable, g, con- trols the bus read operation of the memory. write enable (w). the write enable, w, controls the bus write operation of the memory's com- mand interface. reset/block temporary unprotect (rp). the reset/block temporary unprotect pin can be used to apply a hardware reset to the memory or to temporarily unprotect all blocks that have been protected. a hardware reset is achieved by holding reset/ block temporary unprotect low, v il , for at least t plpx . after reset/block temporary unprotect goes high, v ih , the memory will be ready for bus read and bus write operations after t phel or t rhel , whichever occurs last. see the ready/busy output section, table 18 and figure 13, reset/ temporary unprotect ac characteristics for more details. holding rp at v id will temporarily unprotect the protected blocks in the memory. program and erase operations on all blocks will be possible. the transition from v ih to v id must be slower than t phphh . ready/busy output (rb). the ready/busy pin is an open-drain output that can be used to identify when the memory array can be read. ready/busy is high-impedance during read mode, auto select mode and erase suspend mode. after a hardware reset, bus read and bus write operations cannot begin until ready/busy be- comes high-impedance. see table 18 and figure 13, reset/temporary unprotect ac characteris- tics. during program or erase operations ready/busy is low, v ol . ready/busy will remain low during read/reset commands or hardware resets until the memory is ready to enter read mode. the use of an open-drain output allows the ready/ busy pins from several memories to be connected to a single pull-up resistor. a low will then indicate that one, or more, of the memories is busy. byte/word organization select (byte). the byte/word organization select pin is used to switch between the 8-bit and 16-bit bus modes of the memory. when byte/word organization se- lect is low, v il , the memory is in 8-bit mode, when it is high, v ih , the memory is in 16-bit mode. v cc supply voltage. the v cc supply voltage supplies the power for all operations (read, pro- gram, erase etc.). the command interface is disabled when the v cc supply voltage is less than the lockout voltage, v lko . this prevents bus write operations from ac- cidentally damaging the data during power up, power down and power surges. if the program/ erase controller is programming or erasing during this time then the operation aborts and the memo- ry contents being altered will be invalid. a 0.1 m f capacitor should be connected between the v cc supply voltage pin and the v ss ground pin to decouple the current surges from the power supply. the pcb track widths must be sufficient to carry the currents required during program and erase operations, i cc3 . vss ground. the v ss ground is the reference for all voltage measurements.
m29w160dt, M29W160DB 10/29 bus operations there are five standard bus operations that control the device. these are bus read, bus write, out- put disable, standby and automatic standby. see tables 4 and 5, bus operations, for a summary. typically glitches of less than 5ns on chip enable or write enable are ignored by the memory and do not affect bus operations. bus read. bus read operations read from the memory cells, or specific registers in the com- mand interface. a valid bus read operation in- volves setting the desired address on the address inputs, applying a low signal, v il , to chip enable and output enable and keeping write enable high, v ih . the data inputs/outputs will output the value, see figure 10, read mode ac waveforms, and table 15, read ac characteristics, for details of when the output becomes valid. bus write. bus write operations write to the command interface. a valid bus write operation begins by setting the desired address on the ad- dress inputs. the address inputs are latched by the command interface on the falling edge of chip enable or write enable, whichever occurs last. the data inputs/outputs are latched by the com- mand interface on the rising edge of chip enable or write enable, whichever occurs first. output en- able must remain high, v ih , during the whole bus write operation. see figures 11 and 12, write ac waveforms, and tables 16 and 17, write ac characteristics, for details of the timing require- ments. output disable. the data inputs/outputs are in the high impedance state when output enable is high, v ih . standby. when chip enable is high, v ih , the memory enters standby mode and the data in- puts/outputs pins are placed in the high-imped- ance state. to reduce the supply current to the standby supply current, i cc2 , chip enable should be held within v cc 0.2v. for the standby current level see table 14, dc characteristics. during program or erase operations the memory will continue to use the program/erase supply current, i cc3 , for program or erase operations un- til the operation completes. automatic standby. if cmos levels (v cc 0.2v) are used to drive the bus and the bus is inactive for 150ns or more the memory enters automatic standby where the internal supply current is re- duced to the standby supply current, i cc2 . the data inputs/outputs will still output data if a bus read operation is in progress. special bus operations. additional bus opera- tions can be performed to read the electronic sig- nature and also to apply and remove block protection. these bus operations are intended for use by programming equipment and are not usu- ally used in applications. they require v id to be applied to some pins. electronic signature. the memory has two codes, the manufacturer code and the device code, that can be read to identify the memory. these codes can be read by applying the signals listed in tables 4 and 5, bus operations. block protection and blocks unprotection. each block can be separately protected against acci- dental program or erase. protected blocks can be unprotected to allow data to be changed. there are two methods available for protecting and unprotecting the blocks, one for use on pro- gramming equipment and the other for in-system use. for further information refer to application note an1122, applying protection and unprotec- tion to m29 series flash. table 4. bus operations, byte = v il note: x = v il or v ih . operation e g w address inputs dq15a1, a0-a19 data inpu ts/outputs dq14-dq8 dq7-dq0 bus read v il v il v ih cell address hi-z data output bus write v il v ih v il command address hi-z data input output disable x v ih v ih x hi-z hi-z standby v ih x x x hi-z hi-z read manufacturer code v il v il v ih a0 = v il ,a1=v il ,a9=v id , others v il or v ih hi-z 20h read device code v il v il v ih a0 = v ih ,a1=v il ,a9=v id , others v il or v ih hi-z c4h (m29w160dt) 49h (M29W160DB)
11/29 m29w160dt, M29W160DB table 5. bus operations, byte = v ih note: x = v il or v ih . command interface all bus write operations to the memory are inter- preted by the command interface. commands consist of one or more sequential bus write oper- ations. failure to observe a valid sequence of bus write operations will result in the memory return- ing to read mode. the long command sequences are imposed to maximize data security. the address used for the commands changes de- pending on whether the memory is in 16-bit or 8- bit mode. see either table 7, or 8, depending on the configuration that is being used, for a summary of the commands. read/reset command. the read/reset com- mand returns the memory to its read mode where it behaves like a rom or eprom, unless stated otherwise (see security data command). it also resets the errors in the status register. either one or three bus write operations can be used to issue the read/reset command. if the read/reset command is issued during a block erase operation or following a programming or erase error then the memory will take upto 10 m s to abort. during the abort period no valid data can be read from the memory. issuing a read/reset command during a block erase operation will leave invalid data in the memory. auto select command. the auto select com- mand is used to read the manufacturer code, the device code and the block protection status. three consecutive bus write operations are re- quired to issue the auto select command. once the auto select command is issued the memory remains in auto select mode until another com- mand is issued. from the auto select mode the manufacturer code can be read using a bus read operation with a0 = v il and a1 = v il . the other address bits may be set to either v il or v ih . the manufacturer code for stmicroelectronics is 0020h. the device code can be read using a bus read operation with a0 = v ih and a1 = v il . the other address bits may be set to either v il or v ih . the device code for the m29w160dt is 22c4h and for the M29W160DB is 2249h. the block protection status of each block can be read using a bus read operation with a0 = v il , a1 = v ih , and a12-a19 specifying the address of the block. the other address bits may be set to ei- ther v il or v ih . if the addressed block is protect- ed then 01h is output on data inputs/outputs dq0-dq7, otherwise 00h is output. program command. the program command can be used to program a value to one address in the memory array at a time. the command re- quires four bus write operations, the final write op- eration latches the address and data in the internal state machine and starts the program/erase con- troller. if the address falls in a protected block then the program command is ignored, the data remains unchanged. the status register is never read and no error condition is given. during the program operation the memory will ig- nore all commands. it is not possible to issue any command to abort or pause the operation. typical program times are given in table 9. bus read op- erations during the program operation will output the status register on the data inputs/outputs. see the section on the status register for more details. after the program operation has completed the memory will return to the read mode, unless an error has occurred. when an error occurs the memory will continue to output the status regis- operation e g w address inputs a0-a19 data inpu ts/outputs dq15a1, dq14-dq0 bus read v il v il v ih cell address data output bus write v il v ih v il command address data input output disable x v ih v ih x hi-z standby v ih x x x hi-z read manufacturer code v il v il v ih a0 = v il ,a1=v il ,a9=v id , others v il or v ih 0020h read device code v il v il v ih a0 = v ih ,a1=v il ,a9=v id , others v il or v ih 22c4h (m29w160dt) 2249h (M29W160DB)
m29w160dt, M29W160DB 12/29 ter. a read/reset command must be issued to re- set the error condition and return to read mode. note that the program command cannot change a bit set at '0' back to '1'. one of the erase com- mands must be used to set all the bits in a block or in the whole memory from '0' to '1'. unlock bypass command. the unlock bypass command is used in conjunction with the unlock bypass program command to program the memo- ry. when the access time to the device is long (as with some eprom programmers) considerable time saving can be made by using these com- mands. three bus write operations are required to issue the unlock bypass command. once the unlock bypass command has been is- sued the memory will only accept the unlock by- pass program command and the unlock bypass reset command. the memory can be read as if in read mode. unlock bypass program command. the un- lock bypass program command can be used to program one address in memory at a time. the command requires two bus write operations, the final write operation latches the address and data in the internal state machine and starts the pro- gram/erase controller. the program operation using the unlock bypass program command behaves identically to the pro- gram operation using the program command. a protected block cannot be programmed; the oper- ation cannot be aborted and the status register is read. errors must be reset using the read/reset command, which leaves the device in unlock by- pass mode. see the program command for details on the behavior. unlock bypass reset command. the unlock bypass reset command can be used to return to read/reset mode from unlock bypass mode. two bus write operations are required to issue the unlock bypass reset command. chip erase command. the chip erase com- mand can be used to erase the entire chip. six bus write operations are required to issue the chip erase command and start the program/erase controller. if any blocks are protected then these are ignored and all the other blocks are erased. if all of the blocks are protected the chip erase operation ap- pears to start but will terminate within about 100 m s, leaving the data unchanged. no error condition is given when protected blocks are ignored. during the erase operation the memory will ignore all commands. it is not possible to issue any com- mand to abort the operation. typical chip erase times are given in table 9. all bus read opera- tions during the chip erase operation will output the status register on the data inputs/outputs. see the section on the status register for more details. after the chip erase operation has completed the memory will return to the read mode, unless an error has occurred. when an error occurs the memory will continue to output the status regis- ter. a read/reset command must be issued to re- set the error condition and return to read mode. the chip erase command sets all of the bits in un- protected blocks of the memory to '1'. all previous data is lost. block erase command. the block erase com- mand can be used to erase a list of one or more blocks. six bus write operations are required to select the first block in the list. each additional block in the list can be selected by repeating the sixth bus write operation using the address of the additional block. the block erase operation starts the program/erase controller about 50 m s after the last bus write operation. once the program/erase controller starts it is not possible to select any more blocks. each additional block must therefore be selected within 50 m s of the last block. the 50 m s timer restarts when an additional block is selected. the status register can be read after the sixth bus write operation. see the status register for details on how to identify if the program/erase controller has started the block erase operation. if any selected blocks are protected then these are ignored and all the other selected blocks are erased. if all of the selected blocks are protected the block erase operation appears to start but will terminate within about 100 m s, leaving the data un- changed. no error condition is given when protect- ed blocks are ignored. during the block erase operation the memory will ignore all commands except the erase suspend and read/reset commands. typical block erase times are given in table 9. all bus read opera- tions during the block erase operation will output the status register on the data inputs/outputs. see the section on the status register for more details. after the block erase operation has completed the memory will return to the read mode, unless an error has occurred. when an error occurs the memory will continue to output the status regis- ter. a read/reset command must be issued to re- set the error condition and return to read mode. the block erase command sets all of the bits in the unprotected selected blocks to '1'. all previous data in the selected blocks is lost. erase suspend command. the erase suspend command may be used to temporarily suspend a block erase operation and return the memory to read mode. the command requires one bus
13/29 m29w160dt, M29W160DB write operation. during erase suspend the reset command is ignored. the program/erase controller will suspend within 15 m s of the erase suspend command being is- sued. once the program/erase controller has stopped the memory will be set to read mode and the erase will be suspended. if the erase suspend command is issued during the period when the memory is waiting for an additional block (before the program/erase controller starts) then the erase is suspended immediately and will start im- mediately when the erase resume command is issued. it will not be possible to select any further blocks for erasure after the erase resume. during erase suspend it is possible to read and program cells in blocks that are not being erased; both read and program operations behave as normal on these blocks. reading from blocks that are being erased will output the status register. it is also possible to enter the auto select mode: the memory will behave as in the auto select mode on all blocks until a read/reset command returns the memory to erase suspend mode. erase resume command. the erase resume command must be used to restart the program/ erase controller from erase suspend. an erase can be suspended and resumed more than once. security data command. the security data command can be used to read the security mem- ory block. the security memory block is a block of 256 words that is usually undefined. volume cus- tomers can request that a unique security code is pre-programmed by st into each part. one bus write operation is required to issue the security data command. once the security data command is issued bus read operations read from the se- curity memory block instead of the memory array, until another command is issued. after issuing the security data command from auto select mode a read/reset command will re- turn to auto select mode. an invalid command will return to read mode. valid addresses for the security memory block are given in table 6, security memory block address- es. although the address for the security data command is don't care, it is necessary to choose an address outside the security memory block for correct operation. table 6. security memory block addresses size (words) address range (x8) address range (x16) 256 000000h-0001ffh 000000h-0000ffh
m29w160dt, M29W160DB 14/29 table 7. commands, 16-bit mode, byte = v ih note: x don't care, pa program address, pd program data, ba any address in the block. all values in the table are in hexadecimal. the command interface only uses a1, a0-a10 and dq0-dq7 to verify the commands; a11-a19, dq8-dq14 and dq15 are don't care. dq15a1 is a1 when byte is v il or dq15 when byte is v ih . read/reset. after a read/reset command, read the memory as normal until another command is issued. auto select. after an auto select command, read manufacturer id, device id or block protection status. program, unlock bypass program, chip erase, block erase. after these commands read the status register until the program/ erase controller completes and the memory returns to read mode. add additional blocks during block erase command with additional bus write operations until timeout bit is set. unlock bypass. after the unlock bypass command issue unlock bypass program or unlock bypass reset commands. unlock bypass reset. after the unlock bypass reset command read the memory as normal until another command is issued. erase suspend. after the erase suspend command read non-erasing memory blocks as normal, issue auto select and program com- mands on non-erasing blocks as normal. erase resume. after the erase resume command the suspended erase operation resumes, read the status register until the pro- gram/erase controller completes and the memory returns to read mode. security data. after the security data command read the security memory block. use an address outside the security memory block when issuing the command. command length bus write operations 1st 2nd 3rd 4th 5th 6th addr data addr data addr data addr data addr data addr data read/reset 1x f0 3 555 aa 2aa 55 x f0 auto select 3 555 aa 2aa 55 555 90 program 4 555 aa 2aa 55 555 a0 pa pd unlock bypass 3 555 aa 2aa 55 555 20 unlock bypass program 2x a0papd unlock bypass reset 2 x 90 x 00 chip erase 6 555 aa 2aa 55 555 80 555 aa 2aa 55 555 10 block erase 6+ 555 aa 2aa 55 555 80 555 aa 2aa 55 ba 30 erase suspend 1 x b0 erase resume 1 x 30 security data 1 x b8
15/29 m29w160dt, M29W160DB table 8. commands, 8-bit mode, byte = v il note: x don't care, pa program address, pd program data, ba any address in the block. all values in the table are in hexadecimal. the command interface only uses a1, a0-a10 and dq0-dq7 to verify the commands; a11-a19, dq8-dq14 and dq15 are don't care. dq15a1 is a1 when byte is v il or dq15 when byte is v ih . read/reset. after a read/reset command, read the memory as normal until another command is issued. auto select. after an auto select command, read manufacturer id, device id or block protection status. program, unlock bypass program, chip erase, block erase. after these commands read the status register until the program/ erase controller completes and the memory returns to read mode. add additional blocks during block erase command with additional bus write operations until timeout bit is set. unlock bypass. after the unlock bypass command issue unlock bypass program or unlock bypass reset commands. unlock bypass reset. after the unlock bypass reset command read the memory as normal until another command is issued. erase suspend. after the erase suspend command read non-erasing memory blocks as normal, issue auto select and program com- mands on non-erasing blocks as normal. erase resume. after the erase resume command the suspended erase operation resumes, read the status register until the pro- gram/erase controller completes and the memory returns to read mode. security data. after the security data command read the security memory block. use an address outside the security memory block when issuing the command. command length bus write operations 1st 2nd 3rd 4th 5th 6th addr data addr data addr data addr data addr data addr data read/reset 1x f0 3 aaa aa 555 55 x f0 auto select 3 aaa aa 555 55 aaa 90 program 4 aaa aa 555 55 aaa a0 pa pd unlock bypass 3 aaa aa 555 55 aaa 20 unlock bypass program 2x a0papd unlock bypass reset 2 x 90 x 00 chip erase 6 aaa aa 555 55 aaa 80 aaa aa 555 55 aaa 10 block erase 6+ aaa aa 555 55 aaa 80 aaa aa 555 55 ba 30 erase suspend 1 x b0 erase resume 1 x 30 security data 1 x b8
m29w160dt, M29W160DB 16/29 table 9. program, erase times and program, erase endurance cycles note: 1. t a =25 c, v cc = 3.3v. status register bus read operations from any address always read the status register during program and erase operations. it is also read during erase sus- pend when an address within a block being erased is accessed. the bits in the status register are summarized in table 10, status register bits. data polling bit (dq7). the data polling bit can be used to identify whether the program/erase controller has successfully completed its opera- tion or if it has responded to an erase suspend. the data polling bit is output on dq7 when the status register is read. during program operations the data polling bit outputs the complement of the bit being pro- grammed to dq7. after successful completion of the program operation the memory returns to read mode and bus read operations from the ad- dress just programmed output dq7, not its com- plement. during erase operations the data polling bit out- puts '0', the complement of the erased state of dq7. after successful completion of the erase op- eration the memory returns to read mode. in erase suspend mode the data polling bit will output a '1' during a bus read operation within a block being erased. the data polling bit will change from a '0' to a '1' when the program/erase controller has suspended the erase operation. figure 6, data polling flowchart, gives an exam- ple of how to use the data polling bit. a valid ad- dress is the address being programmed or an address within the block being erased. toggle bit (dq6). the toggle bit can be used to identify whether the program/erase controller has successfully completed its operation or if it has re- sponded to an erase suspend. the toggle bit is output on dq6 when the status register is read. during program and erase operations the toggle bit changes from '0' to '1' to '0', etc., with succes- sive bus read operations at any address. after successful completion of the operation the memo- ry returns to read mode. during erase suspend mode the toggle bit will output when addressing a cell within a block being erased. the toggle bit will stop toggling when the program/erase controller has suspended the erase operation. figure 7, data toggle flowchart, gives an exam- ple of how to use the data toggle bit. error bit (dq5). the error bit can be used to identify errors detected by the program/erase controller. the error bit is set to '1' when a pro- gram, block erase or chip erase operation fails to write the correct data to the memory. if the error bit is set a read/reset command must be issued before other commands are issued. the error bit is output on dq5 when the status register is read. note that the program command cannot change a bit set at '0' back to '1' and attempting to do so may or may not set dq5 at `1'. in both cases, a succes- sive bus read operation will show the bit is still `0'. one of the erase commands must be used to set all the bits in a block or in the whole memory from '0' to '1'. parameter min typ (1) typical after 100k w/e cycles (1) max unit chip erase (all bits in the memory set to `0') 12 sec chip erase 25 25 120 sec block erase (64 kbytes) 0.8 6 sec program (byte or word) 10 200 m s chip program (byte by byte) 25 120 sec chip program (word by word) 12 60 sec program/erase cycles (per block) 100,000 cycles
17/29 m29w160dt, M29W160DB erase timer bit (dq3). the erase timer bit can be used to identify the start of program/erase controller operation during a block erase com- mand. once the program/erase controller starts erasing the erase timer bit is set to '1'. before the program/erase controller starts the erase timer bit is set to '0' and additional blocks to be erased may be written to the command interface. the erase timer bit is output on dq3 when the status register is read. alternative toggle bit (dq2). the alternative toggle bit can be used to monitor the program/ erase controller during erase operations. the al- ternative toggle bit is output on dq2 when the status register is read. during chip erase and block erase operations the toggle bit changes from '0' to '1' to '0', etc., with successive bus read operations from addresses within the blocks being erased. once the operation completes the memory returns to read mode. during erase suspend the alternative toggle bit changes from '0' to '1' to '0', etc. with successive bus read operations from addresses within the blocks being erased. bus read operations to ad- dresses within blocks not being erased will output the memory cell data as if in read mode. after an erase operation that causes the error bit to be set the alternative toggle bit can be used to identify which block or blocks have caused the er- ror. the alternative toggle bit changes from '0' to '1' to '0', etc. with successive bus read opera- tions from addresses within blocks that have not erased correctly. the alternative toggle bit does not change if the addressed block has erased cor- rectly. table 10. status register bits note: unspecified data bits should be ignored. operation address dq7 dq6 dq5 dq3 dq2 rb program any address dq7 toggle 0 0 program during erase suspend any address dq7 toggle 0 0 program error any address dq7 toggle 1 0 chip erase any address 0 toggle 0 1 toggle 0 block erase before timeout erasing block 0 toggle 0 0 toggle 0 non-erasing block 0 toggle 0 0 no toggle 0 block erase erasing block 0 toggle 0 1 toggle 0 non-erasing block 0 toggle 0 1 no toggle 0 erase suspend erasing block 1 no toggle 0 toggle 1 non-erasing block data read as normal 1 erase error good block address 0 toggle 1 1 no toggle 0 faulty block address 0 toggle 1 1 toggle 0
m29w160dt, M29W160DB 18/29 figure 6. data polling flowchart figure 7. data toggle flowchart maximum rating stressing the device above the rating listed in the absolute maximum ratingso table may cause per- manent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not im- plied. exposure to absolute maximum rating con- ditions for extended periods may affect device reliability. refer also to the stmicroelectronics sure program and other relevant quality docu- ments. table 11. absolute maximum ratings note: 1. minimum voltage may undershoot to 2v during transition and for less than 20ns during transitions. read dq5 & dq7 at valid address start read dq7 at valid address fail pass ai03598 dq7 = data yes no yes no dq5 =1 dq7 = data yes no read dq6 start read dq6 twice fail pass ai01370b dq6 = toggle no no yes yes dq5 =1 no yes dq6 = toggle read dq5 & dq6 symbol parameter value unit t bias temperature under bias 50 to 125 c t stg storage temperature 65 to 150 c v io (1) input or output voltage 0.6 to 4 v v cc supply voltage 0.6 to 4 v v id identification voltage 0.6 to 13.5 v
19/29 m29w160dt, M29W160DB dc and ac parameters this section summarizes the operating measure- ment conditions, and the dc and ac characteris- tics of the device. the parameters in the dc and ac characteristics tables that follow, are derived from tests performed under the measurement conditions summarized in table 12, operating and ac measurement conditions. designers should check that the operating conditions in their circuit match the operating conditions when rely- ing on the quoted parameters. table 12. operating and ac measurement conditions figure 8. ac measurement i/o waveform figure 9. ac measurement load circuit table 13. capacitance note: sampled only, not 100% tested. parameter m29w160d unit 70 90 supply voltage (v cc ) 3.0 to 3.6 2.7 to 3.6 v ambient operating temperature (t a ) 40 to 85 40 to 85 c load capacitance (c l ) 30 30 pf input rise and fall times 10 10 ns input pulse voltages 0 to 3 0 to 3 v input and output timing ref. voltages 1.5 1.5 v ai01417 3v 0v 1.5v ai03846 0.8v out c l = 30pf c l includes jig capacitance 3.3k w 1n914 device under test symbol parameter test condition min max unit c in input capacitance v in =0v 6pf c out output capacitance v out =0v 12 pf
m29w160dt, M29W160DB 20/29 table 14. dc characteristics note: sampled only, not 100% tested. symbol parameter test condition min max unit i li input leakage current 0v v in v cc 1 m a i lo output leakage current 0v v out v cc 1 m a i cc1 supply current (read) e=v il ,g=v ih , f = 6mhz 10 ma i cc2 supply current (standby) e=v cc 0.2v, rp = v cc 0.2v 100 m a i cc3 (1) supply current (program/erase) program/erase controller active 20 ma v il input low voltage 0.5 0.8 v v ih input high voltage 0.7v cc v cc + 0.3 v v ol output low voltage i ol = 1.8ma 0.45 v v oh output high voltage i oh = 100 m a v cc 0.4 v v id identification voltage 11.5 12.5 v i id identification current a9 = v id 100 m a v lko (1) program/erase lockout supply voltage 1.8 2.3 v
21/29 m29w160dt, M29W160DB figure 10. read mode ac waveforms table 15. read ac characteristics note: sampled only, not 100% tested. symbol alt parameter test condition m29w160d unit 70 90 t avav t rc address valid to next address valid e=v il , g=v il min 70 90 ns t avqv t acc address valid to output valid e=v il , g=v il max 70 90 ns t elqx (1) t lz chip enable low to output transition g=v il min 0 0 ns t elqv t ce chip enable low to output valid g=v il max 70 90 ns t glqx (1) t olz output enable low to output transition e=v il min 0 0 ns t glqv t oe output enable low to output valid e = v il max 30 35 ns t ehqz (1) t hz chip enable high to output hi-z g = v il max 25 30 ns t ghqz (1) t df output enable high to output hi-z e=v il max 25 30 ns t ehqx t ghqx t axqx t oh chip enable, output enable or address transition to output transition min 0 0 ns t elbl t elbh t elfl t elfh chip enable to byte low or high max 5 5 ns t blqz t flqz byte low to output hi-z max 25 30 ns t bhqv t fhqv byte high to output valid max 30 40 ns ai02922 tavav tavqv taxqx telqx tehqz tglqv tglqx tghqx valid a0-a19/ a1 g dq0-dq7/ dq8-dq15 e telqv tehqx tghqz valid tbhqv telbl/telbh tblqz byte
m29w160dt, M29W160DB 22/29 figure 11. write ac waveforms, write enable controlled table 16. write ac characteristics, write enable controlled note: sampled only, not 100% tested. symbol alt parameter m29w160d unit 70 90 t avav t wc address valid to next address valid min 70 90 ns t elwl t cs chip enable low to write enable low min 0 0 ns t wlwh t wp write enable low to write enable high min 45 50 ns t dvwh t ds input valid to write enable high min 45 50 ns t whdx t dh write enable high to input transition min 0 0 ns t wheh t ch write enable high to chip enable high min 0 0 ns t whwl t wph write enable high to write enable low min 30 30 ns t avwl t as address valid to write enable low min 0 0 ns t wlax t ah write enable low to address transition min 45 50 ns t ghwl output enable high to write enable low min 0 0 ns t whgl t oeh write enable high to output enable low min 0 0 ns t whrl (1) t busy program/erase valid to rb low max 30 35 ns t vchel t vcs v cc high to chip enable low min 50 50 m s ai02923 e g w a0-a19/ a1 dq0-dq7/ dq8-dq15 valid valid v cc tvchel twheh twhwl telwl tavwl twhgl twlax twhdx tavav tdvwh twlwh tghwl rb twhrl
23/29 m29w160dt, M29W160DB figure 12. write ac waveforms, chip enable controlled table 17. write ac characteristics, chip enable controlled note: sampled only, not 100% tested. symbol alt parameter m29w160d unit 70 90 t avav t wc address valid to next address valid min 70 90 ns t wlel t ws write enable low to chip enable low min 0 0 ns t eleh t cph chip enable high to chip enable high min 45 50 ns t dveh t ds input valid to chip enable high min 45 50 ns t ehdx t dh chip enable high to input transition min 0 0 ns t ehwh t wh chip enable high to write enable high min 0 0 ns t ehel t cp chip enable low to chip enable low min 30 30 ns t avel t as address valid to chip enable low min 0 0 ns t elax t ah chip enable low to address transition min 45 50 ns t ghel output enable high chip enable low min 0 0 ns t ehgl t oeh chip enable high to output enable low min 0 0 ns t ehrl (1) t busy program/erase valid to rb low max 30 35 ns t vchwl t vcs v cc high to write enable low min 50 50 m s ai02924 e g w a0-a19/ a1 dq0-dq7/ dq8-dq15 valid valid v cc tvchwl tehwh tehel twlel tavel tehgl telax tehdx tavav tdveh teleh tghel rb tehrl
m29w160dt, M29W160DB 24/29 figure 13. reset/block temporary unprotect ac waveforms table 18. reset/block temporary unprotect ac characteristics note: sampled only, not 100% tested. symbol alt parameter m29w160d unit 70 90 t phwl (1) t phel t phgl (1) t rh rp high to write enable low, chip enable low, output enable low min 50 50 ns t rhwl (1) t rhel (1) t rhgl (1) t rb rb high to write enable low, chip enable low, output enable low min 0 0 ns t plpx t rp rp pulse width min 500 500 ns t plyh (1) t ready rp low to read mode max 10 10 m s t phphh (1) t vidr rp rise time to v id min 500 500 ns ai02931 rb w, rp tplpx tphwl, tphel, tphgl tplyh tphphh e, g trhwl, trhel, trhgl
25/29 m29w160dt, M29W160DB package mechanical figure 14. tsop48 - 48 lead plastic thin small outline, 12 x 20mm, package outline note: drawing is not to scale. table 19. tsop48 - 48 lead plastic thin small outline, 12 x 20mm, package mechanical data symbol millimeters inches typ min max typ min max a 1.20 0.0472 a1 0.05 0.15 0.0020 0.0059 a2 0.95 1.05 0.0374 0.0413 b 0.17 0.27 0.0067 0.0106 c 0.10 0.21 0.0039 0.0083 d 19.80 20.20 0.7795 0.7953 d1 18.30 18.50 0.7205 0.7283 e 11.90 12.10 0.4685 0.4764 e 0.50 0.0197 l 0.50 0.70 0.0197 0.0276 a 0 5 0 5 n48 48 cp 0.10 0.0039 tsop-a d1 e 1n cp b e a2 a n/2 d die c l a1 a
m29w160dt, M29W160DB 26/29 figure 15. so44 - 44 lead plastic small outline, 525 mils body width, package outline note: drawing is not to scale. table 20. so44 - 44 lead plastic small outline, 525 mils body width, package mechanical data symbol millimeters inches typ min max typ min max a 2.42 2.62 0.0953 0.1031 a1 0.22 0.23 0.0087 0.0091 a2 2.25 2.35 0.0886 0.0925 b 0.50 0.0197 c 0.10 0.25 0.0039 0.0098 d 28.10 28.30 1.1063 1.1142 e 13.20 13.40 0.5197 0.5276 e 1.27 0.0500 h 15.90 16.10 0.6260 0.6339 l 0.80 0.0315 a 3 3 n44 44 cp 0.10 0.0039 so-b e n cp b e a2 d c l a1 a h a 1
27/29 m29w160dt, M29W160DB figure 16. lfbga48 - 8 x 6 balls, 0.80 mm pitch, bottom view package outline note: drawing is not to scale. table 21. lfbga48 - 8 x 6 balls, 0.80mm pitch, package mechanical data symbol millimeters inches typ min max typ min max a 1.350 0.0531 a1 0.300 0.200 0.350 0.0118 0.0079 0.0138 a2 1.000 0.0394 b 0.300 0.550 0.0118 0.0217 d 8.000 0.3150 d1 4.000 0.1575 ddd 0.100 0.0039 e 0.800 0.0315 e 9.000 0.3543 e1 5.600 0.2205 fd 2.000 0.0787 fe 1.700 0.0669 sd 0.400 0.0157 se 0.400 0.0157 e1 e d1 d eb sd se a2 a1 a bga-z14 ddd ball oa1o fd fe
m29w160dt, M29W160DB 28/29 part numbering table 22. ordering information scheme devices are shipped from the factory with the memory content bits erased to '1'. for a list of available options (speed, package, etc...) or for further information on any aspect of this de- vice, please contact the st sales office nearest to you. revision history table 23. document revision history example: M29W160DB 90 n 1 t device type m29 operating voltage w=v cc = 2.7 to 3.6v device function 160d = 16 mbit (2mb x8 or 1mb x16), boot block array matrix t = top boot b = bottom boot speed 70 = 70 ns 90 = 90 ns package n = tsop48: 12 x 20 mm m = so44 za = lfbga48: 0.80mm pitch temperature range 1=0to70 c 6=40to85 c optio n t = tape & reel packing date version revision details july 2000 -01 first issue 1/12/01 -02 document type: from product preview to preliminary data
29/29 m29w160dt, M29W160DB information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics products are not authorized for use as critical components in lif e support devices or systems without express written approval of stmicroelectronics. the st logo is registered trademark of stmicroelectronics all other names are the property of their respective owners ? 2001 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - brazil - china - finland - france - germany - hong kong - india - italy - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - u.s.a . www.st.com

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